Project Description

This project contains a pipelined and non-pipelined version of a 5-stages MIPS-compatible CPU. The CPU is programmed using Verilog. Moreover, a testbench with a reference CPU coded using C++ is included. The testbench consists of automatically generated testcases for each required instruciton and several general testcases containing a mixture of different instructions.

The CPU (non-pipelined version) passed 98% of the testcases provided by Imperial. The testbench scored 91% with 5% deducted due to racing condition error.